Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
A conventional flipchip semiconductor package, such as a flexible ball grid array (FBGA), can include a semiconductor die with conductive bumps formed over contact pads on an active surface of the die. The semiconductor die is mounted to a substrate by reflowing the bumps to establish a metallurgical and electrical connection with the substrate. However, unless precise alignment between the bumps and the bond pads is maintained, bridging defects or electrical shorts can occur between the bumps and adjacent conductive traces. In addition, the temperature and pressure during reflow is known to cause the molten bump material to flow laterally and potentially contact adjacent conductive traces, resulting in bridging defects or short circuit conditions. These defects from electrical shorts lower manufacturing yield and increase cost.
Once the semiconductor die has been mounted to the substrate, an underfill material or encapsulant can be deposited between the die and substrate. Another concern with flipchip packages is that a gap between the semiconductor die and substrate may narrow from the reflow temperature and pressure and inhibit the flow of the underfill material. Voids can form in the underfill material between the semiconductor die and substrate. The void defects from an insufficient underfill gap can also lower manufacturing yield and increase cost.
As an illustration of the above defects, FIG. 1a shows a conventional semiconductor die 10 with contact pads 12 formed over active surface 14 of the semiconductor die. An insulating layer 16 is formed over contact pads 12 and active surface 14. A portion of insulating layer 16 is removed to expose contact pads 12. An under bump metallization (UBM) layer 18 is formed over contact pads 12 and insulating layer 16. Conductive pillars 20 are formed over UBM layer 18. Bumps or caps 22 are formed over conductive pillars 20. Semiconductor die 10 is positioned over substrate 24 with bumps 22 aligned to contact pads 26 on the substrate.
In FIG. 1b, semiconductor die 10 is mounted to substrate 24 with bumps 22 metallurgically and electrically connected to contact pads 26 by a reflow or compression. A distance D1 between semiconductor die 10 and substrate 24 represents an underfill gap. During the reflow process, the underfill gap is known to narrow with elevated temperature and pressure causing the molten bump material to flow laterally and potentially contact adjacent conductive traces 28 and create a bridging defect or short circuit condition. Bridging defects are particularly prevalent in fine pitch interconnect applications.
FIGS. 1c and 1d illustrate how misalignment between bumps 22 and contact pads 26 can increase the occurrence of bridging defects. In FIG. 1c, a centerline of bump 22 is offset or misaligned from a centerline of contact pad 26 by a distance D2. As shown in FIG. 1d, bumps 22 may contact an adjacent conductive trace 28 during reflow because of misalignment D2. The bridging defects between bumps 22 and adjacent conductive traces 28 reduce manufacturing yield and increase cost.